# In your .bashrc or .cshrc setenv SYNOPSYS_HOME /tools/synopsys/2021.03 setenv PATH $SYNOPSYS_HOME/bin:$PATH setenv SNPSLMD_LICENSE_FILE 27000@license_server setenv LM_LICENSE_FILE 27000@license_server
report_area -hierarchy > $report_dir/area.rpt report_power -analysis_effort high > $report_dir/power.rpt synopsys design compiler tutorial 2021
The basic design flow using Synopsys Design Compiler involves: # In your
write -format verilog -output outputs/$my_design.v write_sdc outputs/$my_design.sdc $report_dir/area.rpt report_power -analysis_effort high >
Synopsys Design Compiler (DC) is the core tool used in digital IC design to transform high-level RTL code (Verilog or VHDL) into a technology-specific gate-level netlist . In 2021, Synopsys continued to promote Design Compiler NXT